\hypertarget{index_intro_sec}{}\section{About}\label{index_intro_sec}
\begin{DoxyVerb}This driver provides a simple user interface for using
the three DSPI modules on this microcontroller. It provides
high level data transfer functions that can run on either background
or foreground, using Transfer Complete interrupts as needed.

A lot of flexibility is still available to the user via some Macros for
modifying Transfer and Data attributes, or with a lot of different transfer
methods for different needs.

The following code shows how the module is used:
\end{DoxyVerb}



\begin{DoxyCode}
\textcolor{keyword}{struct }\hyperlink{struct___s_p_i___d_r_v}{\_SPI\_DRV} \hyperlink{group__group5_ga2365cce3281e8859c38a37edaced7e89}{SPI}[];          \textcolor{comment}{//SPI variable has to be imported from the SPI Driver module, do
       not forget this line!}
uint16\_t RxData[128];           \textcolor{comment}{//An array for storing received data}
uint16\_t i;                     \textcolor{comment}{//A dummy variable.}


\textcolor{keywordtype}{int} main(\textcolor{keywordtype}{void}) \{
    initModesAndClks();     \textcolor{comment}{//remember to enable DSPI module with PCTL registers, and set
       Sys\_Clk(=Peripheral\_Clock) to 64MHz}
                            \textcolor{comment}{//if you wish to use predefined baud-rates}
    initPeriClkGen();            
    disableWatchdog();           
    \hyperlink{group__group5_gaa3f08b6b790aa1596d6f41a122c17aad}{initialise\_SPI\_DRIVER}();        \textcolor{comment}{//must be called before using the driver}
    enableIrq();
    
    \hyperlink{group__group5_ga2365cce3281e8859c38a37edaced7e89}{SPI}[0].\hyperlink{struct___s_p_i___d_r_v_aead12928b2c4e6898c71c73b32315770}{init}(SPI\_BAUD\_62500, \hyperlink{group__group2_ga9b5018e9d6279fd4f2416aa3891fb106}{SPI\_DELAY\_DEFAULT}); \textcolor{comment}{//Initialise SPI module you
       wish to use, in this example PORT\_A of DSPI0 is defined}
    \hyperlink{group__group5_ga2365cce3281e8859c38a37edaced7e89}{SPI}[1].\hyperlink{struct___s_p_i___d_r_v_aead12928b2c4e6898c71c73b32315770}{init}(SPI\_BAUD\_62500, \hyperlink{group__group2_ga9b5018e9d6279fd4f2416aa3891fb106}{SPI\_DELAY\_DEFAULT}); \textcolor{comment}{//and PORT\_E of DSPI1, and they
       are connected with jumper wires.}
    
    \textcolor{comment}{//Following lines test the driver with different methods and changing}
    \textcolor{comment}{//DSPI modules roles as it goes (master/slave, tx/rx etc..). At the end of the}
    \textcolor{comment}{//program you can check the memory map, @RxData and see if there has been any undesirable behaviours.}
    \textcolor{comment}{//For instance, it is practical for setting right values for the Delay Attributes.}
    
    \hyperlink{group__group5_ga2365cce3281e8859c38a37edaced7e89}{SPI}[1].\hyperlink{struct___s_p_i___d_r_v_a5f87e1c352b3224fe2a6bed5db0ccf12}{listen}(RxData, 6,1);     \textcolor{comment}{//Here listen is running on the background, after each frame
       transfer}
                                    \textcolor{comment}{//an interrupt incerements RX\_Index and waits for the next data to be
       received.}
                                    \textcolor{comment}{//Useful for a slave device waiting for commands.}
    \textcolor{keywordflow}{for}(i=0xA500;i<0xA509;i++)
    \{
        \hyperlink{group__group5_ga2365cce3281e8859c38a37edaced7e89}{SPI}[0].\hyperlink{struct___s_p_i___d_r_v_a247fbfc90fac794d9c14e81848e53443}{write}(&i);           \textcolor{comment}{//Write a single data, runs only on foreground. Can be used to
       send quick commands.}
    \}
    \textcolor{keywordflow}{while} (!(\hyperlink{group__group5_ga2365cce3281e8859c38a37edaced7e89}{SPI}[0].Completed && \hyperlink{group__group5_ga2365cce3281e8859c38a37edaced7e89}{SPI}[1].Completed))\{\}   \textcolor{comment}{//Always wait for things to be completed when
       using background methods.}


    \hyperlink{group__group5_ga2365cce3281e8859c38a37edaced7e89}{SPI}[0].\hyperlink{struct___s_p_i___d_r_v_adca794807f12ed1014f0e08fbf17c695}{listen\_till}((RxData+6), 0x5A1F,1);       \textcolor{comment}{//This time listen method runs until a
       specific data is received.}
                                                    \textcolor{comment}{//Would be practical for using on ascii transmissions
       ending with '\(\backslash\)0'.}
    \textcolor{keywordflow}{for}(i=0x5A00;i<0x5A2F;i++)
    \{
        \hyperlink{group__group5_ga2365cce3281e8859c38a37edaced7e89}{SPI}[1].\hyperlink{struct___s_p_i___d_r_v_a247fbfc90fac794d9c14e81848e53443}{write}(&i);
    \}
    \textcolor{keywordflow}{while} (!(\hyperlink{group__group5_ga2365cce3281e8859c38a37edaced7e89}{SPI}[0].Completed && \hyperlink{group__group5_ga2365cce3281e8859c38a37edaced7e89}{SPI}[1].Completed))\{\}

    
    i=0xD6E1;
    \hyperlink{group__group5_ga2365cce3281e8859c38a37edaced7e89}{SPI}[0].\hyperlink{struct___s_p_i___d_r_v_a086ad89b79b23005b984e80dc5e65b92}{show}(&i,1);                              \textcolor{comment}{//show method, running on the background, places
       a singla data on TX Buffer}
                                                    \textcolor{comment}{//and when the transfer is completed, an interrupt
       updates its flags.}
    \hyperlink{group__group5_ga2365cce3281e8859c38a37edaced7e89}{SPI}[1].\hyperlink{struct___s_p_i___d_r_v_a0394bc0b91f6bb1a769c0f6added863a}{read}(RxData+40);                         \textcolor{comment}{//Read method, receives specific data from a
       slave. Could be used to}
                                                    \textcolor{comment}{//get a chip's status.}
    \textcolor{keywordflow}{while} (!(\hyperlink{group__group5_ga2365cce3281e8859c38a37edaced7e89}{SPI}[0].Completed && \hyperlink{group__group5_ga2365cce3281e8859c38a37edaced7e89}{SPI}[1].Completed))\{\}
    
    i=0x0666;                                       \textcolor{comment}{//Roles are inverted now, to check if any bugs related
       to the driver exists.}
    \hyperlink{group__group5_ga2365cce3281e8859c38a37edaced7e89}{SPI}[1].\hyperlink{struct___s_p_i___d_r_v_a086ad89b79b23005b984e80dc5e65b92}{show}(&i,1);                              \textcolor{comment}{//Methods set the modules to master or to slave
       according to their needs.}
    \hyperlink{group__group5_ga2365cce3281e8859c38a37edaced7e89}{SPI}[0].\hyperlink{struct___s_p_i___d_r_v_a0394bc0b91f6bb1a769c0f6added863a}{read}(RxData+45);
    \textcolor{keywordflow}{while} (!(\hyperlink{group__group5_ga2365cce3281e8859c38a37edaced7e89}{SPI}[0].Completed && \hyperlink{group__group5_ga2365cce3281e8859c38a37edaced7e89}{SPI}[1].Completed))\{\}

    
    \hyperlink{group__group5_ga2365cce3281e8859c38a37edaced7e89}{SPI}[0].\hyperlink{struct___s_p_i___d_r_v_a5f87e1c352b3224fe2a6bed5db0ccf12}{listen}((RxData+50), 4,1);                \textcolor{comment}{//Now both modules are running on the
       background, 'write array' get the next half word}
    \hyperlink{group__group5_ga2365cce3281e8859c38a37edaced7e89}{SPI}[1].\hyperlink{struct___s_p_i___d_r_v_a41173e3adcf94d40c1aaa34767bf638f}{write\_array}((uint16\_t*)\textcolor{stringliteral}{"Coucou!\(\backslash\)0"},4,1); \textcolor{comment}{//when the current one is transmitted and
       'listen' manages the RX array.}
                                                    \textcolor{comment}{//In real situations, it would be absur to transfer
       data between two SPI modules}
                                                    \textcolor{comment}{//on the same chip, so it isn't primal if one of the
       interrupts conflict with the other one.}
                                                    \textcolor{comment}{//(Didn't happen in these tests though. Not even with
       4MHz SCK clock.)}
    \textcolor{keywordflow}{while} (!(\hyperlink{group__group5_ga2365cce3281e8859c38a37edaced7e89}{SPI}[0].Completed && \hyperlink{group__group5_ga2365cce3281e8859c38a37edaced7e89}{SPI}[1].Completed))\{\}

    
    \hyperlink{group__group5_ga2365cce3281e8859c38a37edaced7e89}{SPI}[1].\hyperlink{struct___s_p_i___d_r_v_adca794807f12ed1014f0e08fbf17c695}{listen\_till}((RxData+60), 0,1);           \textcolor{comment}{//Reversed roles.}
    \hyperlink{group__group5_ga2365cce3281e8859c38a37edaced7e89}{SPI}[0].\hyperlink{struct___s_p_i___d_r_v_a41173e3adcf94d40c1aaa34767bf638f}{write\_array}((uint16\_t*)\textcolor{stringliteral}{"The night is dark, and full of terror.\(\backslash\)0\(\backslash\)0"},20,1);
    \textcolor{keywordflow}{while} (!(\hyperlink{group__group5_ga2365cce3281e8859c38a37edaced7e89}{SPI}[1].Completed && \hyperlink{group__group5_ga2365cce3281e8859c38a37edaced7e89}{SPI}[0].Completed))\{\}

    
    \hyperlink{group__group5_ga2365cce3281e8859c38a37edaced7e89}{SPI}[1].\hyperlink{struct___s_p_i___d_r_v_aa5e2288fb7202e84696e40a0e35b16b7}{show\_array}((uint16\_t*)\textcolor{stringliteral}{"Lannisters send their regards."},16,1);    \textcolor{comment}{//These are
       practical for checking delay attributes. If those are}
    \hyperlink{group__group5_ga2365cce3281e8859c38a37edaced7e89}{SPI}[0].\hyperlink{struct___s_p_i___d_r_v_acacca74950b68d3dfeeb4b43d5a17234}{read\_array}(RxData+85,16,0);                                      \textcolor{comment}{//too short and
       error on MSB of frames will occur.Or sometimes repeated frames.}
    \textcolor{keywordflow}{while} (!(\hyperlink{group__group5_ga2365cce3281e8859c38a37edaced7e89}{SPI}[0].Completed && \hyperlink{group__group5_ga2365cce3281e8859c38a37edaced7e89}{SPI}[1].Completed))\{\}                       \textcolor{comment}{//It rarely occurs with
       medium speed ports but right delay amounts are primordial for slow ports.}
    
    \hyperlink{group__group5_ga2365cce3281e8859c38a37edaced7e89}{SPI}[0].\hyperlink{struct___s_p_i___d_r_v_aa5e2288fb7202e84696e40a0e35b16b7}{show\_array}((uint16\_t*)\textcolor{stringliteral}{"Lannisters send their regards."},16,1);
    \hyperlink{group__group5_ga2365cce3281e8859c38a37edaced7e89}{SPI}[1].\hyperlink{struct___s_p_i___d_r_v_acacca74950b68d3dfeeb4b43d5a17234}{read\_array}(RxData+110,16,0);
    \textcolor{keywordflow}{while} (!(\hyperlink{group__group5_ga2365cce3281e8859c38a37edaced7e89}{SPI}[0].Completed && \hyperlink{group__group5_ga2365cce3281e8859c38a37edaced7e89}{SPI}[1].Completed))\{\}
    
    i=0x0A50;
    \hyperlink{group__group5_ga2365cce3281e8859c38a37edaced7e89}{SPI}[1].\hyperlink{struct___s_p_i___d_r_v_a086ad89b79b23005b984e80dc5e65b92}{show}(&i,1);
    i=0xF5AF;
    \hyperlink{group__group5_ga2365cce3281e8859c38a37edaced7e89}{SPI}[0].\hyperlink{struct___s_p_i___d_r_v_aaa043d94a20a9a8b13a062be3944e679}{exchange}(&i,RxData+127);
    \textcolor{keywordflow}{while} (!(\hyperlink{group__group5_ga2365cce3281e8859c38a37edaced7e89}{SPI}[0].Completed && \hyperlink{group__group5_ga2365cce3281e8859c38a37edaced7e89}{SPI}[1].Completed))\{\}


    \textcolor{keywordflow}{while} (1)    \textcolor{comment}{//End of program }
    \{
    \}
\}
\end{DoxyCode}
 